Maximum likelihood carrier phase synchronization in FPGA-based software defined radios

Digital signal processing techniques are applied to maximum likelihood carrier phase synchronization for QPSK and QAM in an all-digital sampled data receiver. To achieve the flexibility required by modern Software Defined Radios (SDR’s), this task must either be performed in a DSP processor (reconfigurable software) or in an FPGA (reconfigurable hardware). This paper describes the design process for an FPGA-based design and summarizes the FPGA resources required for QPSK carrier phase synchronization.